In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits. Some integrated circuits comprise both PNP bipolar transistors and NPN bipolar transistors. The process for manufacturing bipolar transistors in an integrated circuit (sometimes referred to as a control flow process) involves the performance of a number of different types of manufacturing steps.
Most modern bipolar transistors have an intrinsic base and an extrinsic base. The intrinsic base is the actual electrically active base of the transistor. The extrinsic base is a heavily doped region to provide low resistance connection to the intrinsic base from the metal contact. In this way the relationship between the intrinsic base and the extrinsic base is similar to the relationship between the lightly doped drain and the heavily doped drain in modern metal oxide semiconductor (MOS) devices.
It is important that the emitter base junction occur in the extrinsic base. The heavy doping and damage in the extrinsic base can lead to junction leakage and low breakdown voltage. However, it is desirable to have the extrinsic base as close as possible to the emitter base junction in order to reduce the total lateral base resistance of the transistor.
This lateral base resistance is detrimental to the parametric performance of the transistor. Several methods exist to optimize the distance between the emitter base junction and the extrinsic base. One method is to use photolithography. The emitter is aligned to the extrinsic base using a photolithography tool such as a stepper, a step and scan system or a projection aligner.
However, there are several sources of error in this system. Both the emitter and the extrinsic base patterns are subject to variation in their sizes due to the photolithography and/or etch processes used to define them. If the emitter is too small or the extrinsic base too small, the base resistance will be too high. If the emitter is tool large or the extrinsic base is too large, the heavily doped and damaged extrinsic base can infringe on the emitter base junction leading to leakage and low breakdown voltage.
In addition to the size variation problem, there is a more serious problem due to the alignment of the extrinsic base to the emitter. If the extrinsic base is not centered on the emitter, it can lead to both the previously cited problems because the extrinsic base would be too close on one or more sides while being too far away on the opposite side or sides.
In general, alignment systems have approximately three times more variation in alignment error than in size error. The two most commonly applied methods of addressing this problem are to use a more precise stepper or to use a method that allows the extrinsic base to be aligned to the emitter base junction and better control of the respective structure sizes.
However, better alignment tools are very expensive. See, for example, page 2 of http://www.molecularimprints.com/NewsEvents/tech_articles/SPIE05 Molecular Imprints COO paper-final.pdf. Photolithographic tools for the 90 nm technology generation are estimated to cost twenty million dollars ($20,000,000). Photolithographic tools for the 65 nm technology generation are estimated to cost twenty five million dollars ($25,000,000).
The other alternative is to use a method of manufacturing that does not require alignment of the extrinsic base to the emitter base junction. One of the most prevalent methods of manufacturing advanced bipolar transistor devices is the Quasi Self Aligned method. However, this method aligns the extrinsic base to the emitter poly rather than to the emitter base junction and so does not solve the fundamental problem.
International Business Machines (IBM) has provided a self-aligned process which utilizes a local oxidation of silicon (LOCOS) process and a complex stack of oxide, nitride and poly to generate a self-aligned emitter window where the emitter intrinsic base would be formed. However, etching these complex stacks when patterning and removing them can be quite difficult. LOCOS, even with high pressure oxidation requires a high temperature and time. This combination of temperature and time causes undesired diffusion of the intrinsic base doping which in turn degrades the speed of the transistor.
There is a need in the art for an efficient method for manufacturing self-aligned PNP and NPN bipolar transistors that have very low thermal requirements. In particular, there is a need in the art for a method that is capable of efficiently manufacturing such PNP and NPN bipolar transistors in a unified control flow process. A unified control flow process is capable of manufacturing PNP bipolar transistors and NPN bipolar transistors in the same integrated circuit.
The present invention provides an efficient method for manufacturing NPN bipolar transistors and PNP bipolar transistors. An advantageous embodiment of the method of the invention for manufacturing a PNP transistor comprises the steps of forming a P type collector on a substrate, forming a PNP epitaxial base on the P type collector, forming a PNP extrinsic base in the PNP epitaxial base, and forming a PNP emitter in contact with the PNP extrinsic base.
An advantageous embodiment of the method of the invention for manufacturing an NPN transistor comprises the steps the steps of forming an N type collector on a substrate, forming a NPN epitaxial base on the N type collector, forming an NPN extrinsic base in the NPN epitaxial base, and forming an NPN emitter in contact with the NPN extrinsic base.
It is an object of the present invention to provide a method for efficiently manufacturing a self-aligned PNP transistor that has very low thermal requirements.
It is an object of the present invention to provide a method for efficiently manufacturing a self-aligned NPN transistor that has very low thermal requirements.
It is another object of the present invention to provide a method for efficiently combining the manufacturing steps for PNP transistors and the manufacturing steps for NPN transistors in a unified control flow process.
It is another object of present invention to manufacture PNP transistors and NPN transistors in a manner that minimizes the number of required manufacturing process steps.
It is another object of the present invention to provide a method for forming a PNP extrinsic base in a PNP epitaxial base and forming a PNP emitter in contact with the PNP extrinsic base.
It is another object of the present invention to provide a method for forming an NPN extrinsic base in an NPN epitaxial base and forming an NPN emitter in contact with the NPN extrinsic base.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those persons who are skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Persons who are skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Persons who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those persons of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as future uses, of such defined words and phrases.